Clock and Data Recovery (CDR) circuits are important receiver (RX) components in serializer/de-serializer (SerDes) designs, such as high speed serial input/output (I/O) designs. In order to transmit serial data at a high speed, the CDR extracts phase information from received serial data and generates a clock in synchronization with the data—i.e., outputs recovered clock and data signals for the RX component.
The ability to generate an accurate clock signal from an incoming data stream requires a sampling position that yields the lowest bit error rate (BER). For high-speed serial data transmissions, baud rate phase detection is frequently used rather than over-sampling processes due to its simplicity and low power consumption.
The principle of known baud rate phase detection processes, such as Mueller-Müller phase detection, is to detect the best sampling position based on the combined pulse response through the use of error information, which is defined by comparing the incoming data signal to a reference threshold at the sampler input; however, for interconnections having high speeds or high insertion loss (e.g., due to a long channel), these known baud rate phase detection processes produce sub-optimal samples, leading to incorrect clock and data recovery results.